The conventional manufacture of circuitized substrates such as printed circuit boards and chip carriers, especially those of the multi-layered type, involves many individual processes such as etching, plating, lamination, drilling, testing, inspection, etc. Typically, these processes are performed at different locations within the manufacturing facility, requiring shipment of partially completed substrates from one station to another at such different locations. Such transfer is costly and time-consuming, especially when involving multi-layered products, the most common of boards sold today in view of increased operational demands for the products (e.g., computer servers, mainframes, etc.) in which such boards are implemented. In these boards, the board typically consists of parallel, planar, alternating inner layers of insulating substrate material and conductive metal. The exposed outer sides of the laminated structure are often provided with circuit patterns, as with double-sided boards, and the metal inner layer or layers typically contain circuit patterns, or, in the case of internal power planes, layers that are substantially solid. These latter layers also often include clearance openings or other openings if desired.
In multilayer printed circuit boards, it is necessary to provide conductive interconnections between the various conductive layers or sides of the board. This is commonly achieved by providing metallized, conductive thru holes in the board which communicate with the sides and layers requiring electrical interconnection. For some applications, it is desired that electrical connection be made between all or almost all of the conductive layers. It is often desired to also provide electrical connection between the circuitry on one face of the board and one or more of the inner circuit layers. In those cases, “blind vias”, passing only part way through the board, are provided. In still another case, such multilayered boards often require internal “vias” which are located entirely within the board's structure and covered by external layering, including both dielectric and conductive. Such internal “vias” are typically formed within a sub-part structure of the final board and then combined with other layers during final lamination of the board. The term “conductive thru-hole” as used in the art may thus include both thru holes that pass entirely through the board (also referred to in the printed circuit field as plated thru holes or PTH's), “blind vias” which extend from an external surface of the board into a specified conductive layer of the board, as well as an “internal via” which is internally “captured” by the board's outer layers.
To provide the desired circuit pattern on the substrate, a variety of even more manufacturing processes are required, examples being those which fall into the broad categories of “subtractive” or “additive” techniques. Common to subtractive processing is the need to etch away (or subtract) metal to expose substrate surface in areas where no circuitry is desired. Additive processes, on the other hand, begin with exposed substrate surfaces (or thin commoning metallization layers for additive electroplate) and build up thereon of metallization in desired areas, the desired areas being those not masked by a previously-applied pattern of plating resist material (e.g., called photo-resist in the printed circuit board field). In conventional manufacture, such plating occurs in a separate department or location of the facility.
Typically, thru-holes are drilled (including mechanically or more recently using lasers) or punched into or through the substrate at desired locations. Drilling or punching provides newly exposed interior surfaces including via barrel surfaces and via peripheral entry surfaces. The dielectric substrate, comprising a top surface, a bottom surface, and at least one exposed via hole surface, consisting partly or entirely of insulating material, is then metallized, generally by utilization of electroless metal depositing techniques, albeit other deposition processes are also known in the field. The formation of such thru-holes also typically occurs at a separate, different location within the manufacturing facility.
In the manufacture of circuitized substrates such as printed circuit boards, one or more dielectric sheets are employed for the substrate. These are typically of an organic material, such as fiberglass-reinforced epoxy resin (also referred to in the field as, simply, “FR4”), polytetrafluoroethylene (e.g., Teflon, a trademark of E.I. DuPont deNemours Company), Driclad material (Driclad is a trademark of the assignee of this invention, Endicott Interconnect Technologies, Inc.), etc. It is also known to utilize photo-imageable materials for such dielectric layers. Typically, when the dielectric materials for the structure are of a photo-imageable material, the material is photo-imaged or photo-patterned, and developed to reveal the desired circuit pattern, including the desired opening(s) as defined herein, if required. The dielectric material may be curtain-coated or screen-applied, or it may be supplied as dry film. Final cure of the photo-imageable material provides a toughened base of dielectric on which the desired electrical circuitry is formed. An example of a particularly useful photo-imageable dielectric is ASMDF (Advanced Soldermask Dry Film). This composition, which is further described in U.S. Pat. No. 5,026,624, which issued Jun. 25, 1991, and U.S. Pat. No. 5,300,402, which issued Apr. 25, 1994, includes a solids content of from about 86.5 to about 89%, such solids comprising: about 27.44% PKHC, a phenoxy resin; 41.16% of Epirez 5183, a tetrabromobisphenol A; 22.88% of Epirez SU-8, an octafunctional epoxy bisphenol A formaldehyde novolac resin; 4.85% UVE 1014 photo-initiator; 0.07% ethylviolet dye; 0.03% FC 430, a fluorinated polyether nonionic surfactant from 3M Company; 3.85% Aerosil 380, an amorphous silicon dioxide from Degussa to provide the solid content. A solvent is present from about 11 to about 13.5% of the total photo-imageable dielectric composition. When such photo-imageable dielectric materials are used, these also are applied typically at a separate station within the manufacturing facility, often distant from the others. As indicated above, this invention relates particularly to substrates which utilize one or more photo-imageable dielectric layers as part thereof.
Since the dielectric substrate is nonconductive, in order to plate on the substrate, the substrate is typically “seeded” and one of the above two plating processes then occurs. Typically, these sheets are provided as individual, thin layers of rectangular shape and “stacked” with other layers, including conductive layers, to form the multi-layered final structure, except in the case, of course, of when photo-imageable materials are used in which case these are coated onto the desired sub-composite and, when completed, also stacked up with others sub-composites to form the final multi-layered structure.
Still further manufacturing steps include the afore-mentioned inspection and testing operations. Often, inspections mandate the use of highly precise equipment such as programmed television cameras, in addition to manual inspection, while testing typically is accomplished with complex test apparatus requiring a skilled professional to operate. Both of these operations are also usually performed at different locations in the facility from other manufacturing operations such as defined above.
Examples of methods of making boards, including providing same with such thru holes, are shown and described in the following U.S. Letters Patents, as are examples of various types of boards produced by such methods (including those with photo-imageable dielectric layers as part thereof):
6,015,520Method For Filling Holes in Printed Wiring Boards6,073,344Laser Segmentation of Plated Through-Hole SidewallsTo Form Multiple Conductors6,175,087Composite Laminate Circuit Structure And Method OfForming The Same6,188,027Protection of a Plated Through Hole From Chemical Attack6,204,453Two Signal One Power Plane Circuit Board6,349,871Process For Reworking Circuit Boards6,388,204Composite Laminate Circuit Structure And Methods OfInterconnecting The Same6,479,093Composite Laminate Circuit Structure And Methods OfInterconnecting The Same6,493,861Interconnected Series of Plated Through Hole Vias andMethod of Fabrication Therefore6,495,239Dielectric Structure And Method Of Formation6,521,844Through Hole In A Photoimageable Dielectric Structure WithWired And Uncured Dielectric6,626,196Arrangement and Method For Degassing Small-High AspectRatio Drilled Holes Prior To Wet Chemical Processing6,628,531Multi-Layer and User-Configurable Micro-PrintedCircuit Board6,630,630Multilayer Printed Wiring Board and ItsManufacturing Method6,630,743Copper Plated PTH Barrels and Methods For Fabricating6,631,558Blind Via Laser Drilling System6,631,838Method For Fabricating Printed Circuit Board6,638,690Method For Producing Multi-Layer Circuits6,638,858Hole Metal-Filling Method6,750,405Two Signal One Power Plane Circuit Board
Various attempts have been made to manufacture at least some parts of circuit boards using what might be referred to as a continuous process. Examples of some of these processes are described below.
In U.S. Pat. No. 4,372,800, issued Feb. 8, 1983, there is described a “continuous” process for producing reinforced resin laminates comprising the steps of impregnating a fibrous substrate with a liquid resin (allegedly free of volatile solvent and capable of curing without generating liquid and gaseous by-products), laminating a plurality of the resin-impregnated substrates into a unitary member, sandwiching the laminate between a pair of covering sheets, and curing the laminate between said pair of covering sheets, without applying appreciable pressure. The patent discusses adjusting the final resin content in the resin impregnated substrate at 10 to 90% by weight, based on the total weight of the impregnated substrate.
In U.S. Pat. No. 4,557,784, issued Dec. 10, 1985, there is described a metal clad laminate produced in “continuous” manner by impregnating a plurality of fibrous substrate with a curable liquid resin, combining the plurality of substrates together and simultaneously laminating a metal foil onto at least one side of said substrates, and curing the laminate. This patent discusses the steps of applying an adhesive onto the metal foil to form a film and heating the film in situ continuously prior to step of the laminating of said metal foil.
In U.S. Pat. No. 4,579,612, issued Apr. 1, 1986, there is described the formation of an “electro-laminate” made of a core of insulating material webs with a high purity electrolytic copper foil on at least one side of the core, for use as a circuit board in electronic equipment. The web of insulating material and the copper foil are led from supply rolls to a laminating machine in out-of-contact relation. Prior to its introduction into the laminating machine, the copper foil is heated to the temperature of the laminating operation so that it is at its maximum thermally expanded length when it contacts the insulating material webs. Further, dust is removed from the copper foil as it enters the laminating machine. The webs and copper foil are moved at the same speed through the laminating machine. After pressing the electro-laminate in the laminating machine, it is moved through a cooling device. Subsequently, the electro-laminate can be wound in a roll or cut into individual lengths.
In U.S. Pat. No. 4,659,425, issued Apr. 21, 1987, there is described a “continuous” method wherein a coating of a solvent-free thermosetting resin is applied to the surface of a metal foil. This resin-coated foil is advanced into contact with a reinforcing cloth sheet layer to form a foil/cloth assembly. The assembly is continuously conveyed between a pair of endless belts revolving in opposite directions with mutually facing surfaces, the belts being heated to the curing temperature of the resin whereby the belts are pressed against the assembly to continuously compact the assembly and cure the resin to form a composite product which can then be circuitized. This partial process does not include many of the essential steps such as defined above which are necessary for boards of more complex construction, especially those needing conductive thru-holes as part thereof.
In U.S. Pat. No. 4,902,610, issued Feb. 20, 1990, there is described a process for forming a multilayer printed circuit board comprising providing a non-conductive carrier having a circuit pattern over at least one of its surfaces, applying a first permanent photo dielectric coating over the circuit pattern, exposing the permanent photo dielectric coating to activating radiation in an image pattern comprising an array of openings at locations where interconnections are desired and developing the imaged photo dielectric coating to provide photo-formed openings, selectively providing an electro-less plating catalyst within the photo-formed openings and plating electro-less copper onto the plating catalyst to render the photo-formed openings conductive, applying a permanent photo mask over the metallized layer of interconnections, exposing the permanent photo mask to activating radiation in an image pattern comprising an array of conductors and interconnections at desired locations, developing the imaged photo mask to provide photo-formed conductor lines where conductors are desired and photo-formed openings where interconnections are desired and selectively providing an electro-less plating catalyst within the photo-formed openings and plating electro-less copper onto the electro-less plating catalyst to render the photo-formed openings conductive and repeating the process sequentially until the desired number of layers are formed.
In U.S. Pat. No. 5,153,986, issued Oct. 13, 1992, there is described a method of fabricating a multilayer electronic circuit package. The multilayer circuit package has at least one layer that is a circuitized, polymer encapsulated metal core. According to the method of the invention a metal foil is provided for the metal core of the layer. This metal core foil may be provided as a single unit or in a roll to roll, process. The thru holes are drilled, etched, or punched through the metal foil. An adhesion promoter is then applied to the perforate metal foil for subsequent adhesion of polymer to the foil. The dielectric polymer is then applied to the perforate metal foil core by vapor depositing, chemical vapor depositing, spraying or electrophoretically depositing, a thermally processable dielectric polymer or precursor thereof onto exposed surfaces of the perforate metal foil including the walls of the thru holes. The dielectric polymer or precursor thereof is then thermally processed to form a conformal dielectric, polymeric coating on surfaces of the perforate metal foil, including the interior surfaces of the thru holes. This dielectric, polymeric coating may then be circuitized, and coated with an adhesive for lamination to the next adjacent layer. After lamination, one or more chips are attached to the completed package.
In U.S. Pat. No. 6,388,202, issued May 14, 2002, there is described a high density multi-layer printed circuit board formed by building additional dielectric and metallization layers over a central core of conventional laminate construction. The central core has a metallization pattern on at least one surface. A photo-imaged dielectric layer is deposited on one side of the central core and overlies the metallization pattern. Vias are formed in this dielectric layer using a photo-imaging process, and an additional metallization pattern on this layer is electrically connected to the underlying metallization pattern through the vias. A non-photo-imageable dielectric layer is deposited on the other side of the central core. Vias are formed in this dielectric layer by a laser drilling process, and an additional metallization pattern on this layer is electrically connected to an underlying metallization pattern through these laser drilled vias.
In U.S. Pat. No. 6,391,210, issued May 21, 2002, there is described a process for the manufacture of a multi-level circuit board having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photo-imageable dielectric over the first-level circuitry pattern; exposing the permanent photo-imageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process described comprises making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured using photo-imaging processes.
In U.S. Pat. No. 6,500,349, issued Dec. 31, 2002, there is described a “continuous” process for forming multilayer circuit structures which includes applying and curing a film forming polymer onto the matte side of a copper foil. The opposite (shiny) side of the foil is cleaned, and applied with a photoresist which is then dried. The photo-resist is exposed, and developed to remove the non-image areas, while leaving the image areas. The foil under the removed non-image area is then etched to form a copper pattern, and the remaining photo-resist is removed. The foil is then cut into sections, and then punched with registration holes. The copper pattern is then treated with a bond enhancing treatment, inspected for defects, and laminated onto a substrate to form a multilayered circuit structure.
The present invention represents a new and unique method of forming circuitized substrates having conductive thru holes therein, in comparison to those above and other processes known in the art. Significantly, the method as defined herein involves the making of a circuitized substrate beginning from providing layers of conductor and dielectric material on through circuitizing, all on a continuous format, and then segmenting the circuitized elements to produce individual substrates. Such substrates can then be bonded, e.g., laminated, to other similar substrates to form a larger, multi-layered structure. It is believed that such a method will represent a significant advancement in the art.